New PDF release: ESD Protection Device and Circuit Design for Advanced CMOS

Posted On April 21, 2018 at 3:04 am by / Comments Off on New PDF release: ESD Protection Device and Circuit Design for Advanced CMOS

By Oleg Semenov

ISBN-10: 1402083009

ISBN-13: 9781402083006

ESD defense equipment and Circuit layout for complicated CMOS applied sciences is meant for training engineers operating within the parts of circuit layout, VLSI reliability and trying out domain names. because the difficulties linked to ESD disasters and yield losses develop into major within the sleek semiconductor undefined, the call for for graduates with a easy wisdom of ESD can also be expanding. this present day, there's a major call for to teach the circuits layout and reliability groups on ESD matters. This e-book attempts to handle the ESD layout and implementation in a scientific demeanour. A layout process related to machine simulators in addition to circuit simulator is hired to optimize machine and circuit parameters for optimum ESD in addition to circuit functionality. this system, defined in ESD safety gadget and Circuit layout for complex CMOS applied sciences has ended in a number of profitable ESD circuit layout with very good silicon effects and demonstrates its strengths.

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Extra info for ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Example text

Thesis, 1999. [6] J. -B. Huang and G. Wang, “ESD protection design for advanced CMOS,” Proc. of SPIE, vol. 4600, pp. 123–131, 2001. [7] J. E. Vinson and J. J. Liou, “Electrostatic discharge in semiconductor devices: protection techniques,” Proc. of the IEEE, vol. 88, No. 12, pp. 1878–1900, 2000. [8] H. A. Gieser, “ESD testing: HBM to very fast TLP”, tutorial presented at the ISREF 2004. [9] D. W. Greve, “Programming mechanism of polysilicon resistor fuses,” IEEE Trans. , vol. ED-29, No. 4, pp. 719–724, 1982.

Eng, and K. P. MacWilliams, “Quantifying ESD/EOS latent damage and integrated circuit leakage currents,” EOS/ESD Symposium, pp. 304–310, 1995. [16] R. Renninger, M. Jon, D. Ling, et al. “A field induced charged-device model simulator,” EOS/ESD Symposium, pp. 59–71, 1989. [17] S. H. Voldman, “The impact of technology scaling on ESD robustness of aluminum and copper interconnects in advanced semiconductor technologies,” IEEE Trans. on Components, Packaging & Manufacturing Technology, Part C (Manufacturing), vol.

Robinson-Hahn, M. Farris, J. Scanlon, D. Lin, J. Veltri, and G. Groeseneken, “Recommendations to furter improvements of HBM ESD component level test specifications,” EOS/ESD Symposium, pp. 40–53, 1996. Chapter 3 ESD DEVICES FOR INPUT/OUTPUT PROTECTION 1. INTRODUCTION As discussed in Chapter 2, ESD is a very high current event. Therefore, ESD protection circuits should be able to handle a large amount of current without being destroyed. A number of semiconductor devices can be used to safely sink (source) this current; hence can be used as ESD protection circuit.

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ESD Protection Device and Circuit Design for Advanced CMOS Technologies by Oleg Semenov

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